As is known by those skilled in the art, memory line decoder drivers provide for driving associated rows or columns on the basis of a selection signal and address signals by which the associated row or column address is coded.
Like other nonvolatile memory components, memory line decoder drivers present conflicting requirements of low current consumption and high reading speed. This is because the speed at which the rows and columns in a memory are addressed (and hence the speed of the reading phase) increases with increases in the current charging the row or column capacitance, thus resulting in increased current consumption.
The following description applies to both row and column decoder drivers, but for simplicity reference will be made to a row decoder driver only. To enable a clearer understanding of the problem the invention addresses, a description will first be given of a typical row decoder driver arrangement as known to those skilled in the art, with reference to FIG. 1 in which the driver is indicated as a whole by 1.
As shown in FIG. 1, driver 1 comprises a NAND circuit 2 with three inputs for coding the address of the row to be addressed (signals A, B and C); a selection transistor 3 interposed between the output of NAND circuit 2 and a node 4, and the gate terminal of which is supplied with a selection signal Pi; a final inverter 5 with its input connected to node 4 and its output 7 connected to the word line WL associated with the driven row; and a P channel pull-up transistor 6 interposed between a supply line VPC and node 4, and the gate terminal of which is supplied with a voltage control signal V1.
In the FIG. 1 circuit, pull-up transistor 6 is required to maintain the input of final inverter 5 biased when selection signal Pi is maintained low to deselect the group of rows addressed by Pi (the same selection signal Pi is also supplied to other rows, typically sixteen in all). When selection signal Pi is switched to low, selection transistor 3 is disabled, and, in the absence of a pull-up transistor, would leave the input of final inverter 5 floating. Pull-up transistor 6 provides for connecting node 4 to supply line VPC, thereby biasing the input of final inverter 5.
Pull-up transistor 6 is driven in two ways presently known in the art. In a first known solution as shown in FIG. 1, signal V1 is such as to keep pull-up transistor 6 always on. In a second known solution as shown in FIG. 2, signal V1 switches according to whether the associated row is selected or deselected, and more specifically turns off pull-up transistor 6 if the associated row is selected.
In FIG. 2 (in which the same parts as in FIG. 1 are indicated using the same numbering system), the gate terminal of pull-up transistor 6 is connected to the output of an inverter 10, the input of which is connected to node 4.
Both the solutions described above present drawbacks.
Both solutions have zero current consumption under static conditions at the end of the address switching transient when signals A, B and C are high but the associated row is not selected by signal Pi becoming high. However, both signals behave differently at the end of the row selection transient when signals A, B and C and selection signal Pi are all high. Then, first solution presents a current path between pull-up transistor 6 (on), selection transistor 3 and the N channel transistors (not shown) typically forming NAND circuit 2; which current path, in view of the large size of the driver components for ensuring fast operation, results in more than negligible current consumption.
In the second solution (FIG. 2 circuit) on the other hand, following the row selection transient (node 4 low), pull-up transistor 6 is turned off so that current consumption is zero under static conditions. The second solution, however, requires the use of a carefully designed feedback circuit which can present operating problems in the event of a wide variation in the supply voltage of driver 1 and involves a complex layout.
Therefore, there is a need in the art for a decoder driver bias circuit designed to overcome the drawbacks of known solutions, and which in particular is such as to provide the low current consumption of the decoder driver under static conditions, and high-speed switching during the selection transient.